We present a reconfiguration DFT methodology for evaluating the static performance of a charge redistribution analog-to-digital converter. During the test mode, we reconfigure the ADC to operate as an capacitor ratio converter and measure the primary capacitor ratios which determine the transition voltages. Based on these estimated transition voltages the static performance of the converter under test can be derived. To validate the methodology we designed and fabricated a 11-bit charge redistribution ADC with the reconfiguration DFT technique in a 1.2μm CMOS process. The technique was used to reconstruct the integral (INL) and differential non-linearity (DNL) errors using a digital only tester. The INL and DNL results were verified with analog/digital bench equipment.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Dec 1 2004|
|Event||Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC - Orlando, FL, United States|
Duration: Oct 3 2004 → Oct 6 2004