The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range -7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer. As a ripple carry adder (RCA) consumes the least power among all the existing adder architectures, we have implemented the 4-bit adder as a RCA. Previous incrementers were implemented as ripple counters. In this paper we propose a novel incrementer which is faster than a ripple counter based incrementer. Hence, it can be operated at a reduced voltage resulting in considerable power reduction. The incrementer is implemented using multiplexers, AND gates and TSPC registers. The ripple-counter correlator and the proposed incrementer correlator were laid out in MAGIC using 0.5 μ CMOS technology followed by power estimation using HSPICE. It is shown that the proposed architecture requires 50% less power than a ripple counter based design.
|Original language||English (US)|
|Number of pages||8|
|Journal||Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology|
|State||Published - Aug 2003|
Bibliographical noteFunding Information:
The authors would like to thank Dr. S. Sriram and Dr. M. Kuhlmann for numerous useful discussions. This research was supported by Defense Advanced Research Project Agency under contract number DA/DABT63-96-C-0050, and was carried out at the University of Minnesota.