A memory optimized mersenne-twister random number generator

Naman Saraf, Kia Bazargan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Random number generators (RNGs) are an integral component of numerous stochastic simulation methods, with applications in diverse scientific disciplines. Recently, stochastic simulation methods are being increasingly implemented on FPGAs for improved performance. Consequently, efficient RNG implementations are essential to successfully realize stochastic simulation methods on FPGAs. We present a memory optimized architecture of the prominent Mersenne-Twister RNG (MT-RNG) for efficient implementation on FPGAs. Our approach leverages the different memory constructs available on an FPGA device to reduce the memory requirements of our architecture by upto 50% over existing designs in published literature. Furthermore, we perform an out-of-order computation of random numbers to reduce the hardware area of our MT-RNG implementation, and compare the hardware metrics of our proposed architecture with the existing implementations on different FPGA platforms.

Original languageEnglish (US)
Title of host publication2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages639-642
Number of pages4
Volume2017-August
ISBN (Electronic)9781509063895
DOIs
StatePublished - Sep 27 2017
Event60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States
Duration: Aug 6 2017Aug 9 2017

Other

Other60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
Country/TerritoryUnited States
CityBoston
Period8/6/178/9/17

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