A miniature 2 mW 4 bit 1.2 GS/s delay-line-based ADC in 65 nm CMOS

Yahya M. Tousi, Ehsan Afshari

Research output: Contribution to journalArticlepeer-review

50 Scopus citations


A delay-line-based analog-to-digital converter for high-speed applications is introduced. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window. The effects of quantization noise, jitter, and mismatch are discussed. We show that because of the averaging mechanism of the delay-line, this structure is more power efficient in the presence of noise and mismatch in deep sub-micron CMOS. To show the feasibility of this approach, a 4 bit 1.2 GS/s ADC is designed and fabricated in 65 nm CMOS in an active area of 110 mμ×105 μm. The measured INL and DNL of the ADC are below 0.8 bits and 0.5 bits and it achieves an SNDR of 20.4 dB at Nyquist rate. This delay-line-based ADC consumes 2 mW of power from a 1.2 V supply resulting in 196 fJ/conversion step without using any calibration or post-processing.

Original languageEnglish (US)
Article number5983413
Pages (from-to)2312-2325
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Issue number10
StatePublished - Oct 1 2011


  • Analog-to-digital converter
  • CMOS
  • delay-cell
  • delay-line
  • low-power
  • scaling
  • time-to-digital conversion

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