@inproceedings{fa7e2c6498ae41f49d51edf5a8bf09e2,
title = "A multi-story power delivery technique for 3D integrated circuits",
abstract = "Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some interesting facts and design challenges. A multi-story power delivery technique that can reduce the worst case DC noise by 45% and lower the overhead power consumed in the power supply network by 65% is proposed. A test chip layout in an SOI process, showing a 5.3% area overhead, demonstrates the feasibility of the scheme.",
keywords = "3D chip, Multi-story, Power delivery, Power supply noise",
author = "Pulkit Jain and Kim, {Tae Hyoung} and John Keane and Kim, {Chris H.}",
year = "2008",
doi = "10.1145/1393921.1393940",
language = "English (US)",
isbn = "9781605581095",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
pages = "57--62",
booktitle = "ISLPED'08",
note = "ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design ; Conference date: 11-08-2008 Through 13-08-2008",
}