A multi-story power delivery technique for 3D integrated circuits

Pulkit Jain, Tae Hyoung Kim, John Keane, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

45 Scopus citations

Abstract

Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some interesting facts and design challenges. A multi-story power delivery technique that can reduce the worst case DC noise by 45% and lower the overhead power consumed in the power supply network by 65% is proposed. A test chip layout in an SOI process, showing a 5.3% area overhead, demonstrates the feasibility of the scheme.

Original languageEnglish (US)
Title of host publicationISLPED'08
Subtitle of host publicationProceedings of the 2008 International Symposium on Low Power Electronics and Design
Pages57-62
Number of pages6
DOIs
StatePublished - Dec 17 2008
EventISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design - Bangalore, India
Duration: Aug 11 2008Aug 13 2008

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
CountryIndia
CityBangalore
Period8/11/088/13/08

Keywords

  • 3D chip
  • Multi-story
  • Power delivery
  • Power supply noise

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