Approximate computing is a promising approach for low-power IC design and has recently received considerable research attention. To accommodate dynamic levels of approximation, a few accuracy-configurable adder (ACA) designs have been developed in the past. However, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. Some of these designs include error detection and correction circuitry, which further increase the area. In this paper, we investigate a simple ACA design that contains no redundancy or error detection/correction circuitry and uses very simple carry prediction. The simulation results show that our design dominates the latest previous work on accuracy-delay-power tradeoff while using 39% lower area. In the best case, the iso-delay power of our design is only 16% of accurate adder regardless of degradation in accuracy. One variant of this design provides finer-grained and larger tunability than that of the previous works. Moreover, we propose a delay-adaptive self-configuration technique to further improve the accuracy-delay-power tradeoff. The advantages of our method are confirmed by the applications in multiplication and discrete cosine transform computing.
|Original language||English (US)|
|Number of pages||14|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Jun 2018|
Bibliographical noteFunding Information:
Manuscript received June 2, 2017; revised October 20, 2017 and December 25, 2017; accepted January 16, 2018. Date of publication February 28, 2018; date of current version May 22, 2018. This work was supported by NSF under Grant CCF-1255193, Grant CCF-1525749, and Grant CCF-1525925. (Corresponding author: Wenbin Xu.) W. Xu and J. Hu are with the Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843 USA (e-mail: firstname.lastname@example.org; email@example.com).
- Accuracy-configurable adder (ACA)
- approximate computing
- delay-adaptive reconfiguration (DAR)
- low-power design