A study on the performance, complexity tradeoffs of block turbo decoder design

Zhipei Chi, Leilei Song, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

In this paper, results from a study of the tradeoffs between VLSI implementation complexity and performance of block turbo decoder are presented. Specifically, we address low complexity design strategies on choosing the scaling factor of the log extrinsic information, reducing the number of hard decision decodings and reducing the complexity of general hard-decision BCH decoders when soft-decision decodings are utilized.

Original languageEnglish (US)
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages65-68
Number of pages4
DOIs
StatePublished - Dec 1 2001
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: May 6 2001May 9 2001

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume4

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period5/6/015/9/01

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