TY - GEN
T1 - A study on the performance, complexity tradeoffs of block turbo decoder design
AU - Chi, Zhipei
AU - Song, Leilei
AU - Parhi, Keshab K
PY - 2001
Y1 - 2001
N2 - In this paper, results from a study of the tradeoffs between VLSI implementation complexity and performance of block turbo decoder are presented. Specifically, we address low complexity design strategies on choosing the scaling factor of the log extrinsic information, reducing the number of hard decision decodings and reducing the complexity of general hard-decision BCH decoders when soft-decision decodings are utilized.
AB - In this paper, results from a study of the tradeoffs between VLSI implementation complexity and performance of block turbo decoder are presented. Specifically, we address low complexity design strategies on choosing the scaling factor of the log extrinsic information, reducing the number of hard decision decodings and reducing the complexity of general hard-decision BCH decoders when soft-decision decodings are utilized.
UR - http://www.scopus.com/inward/record.url?scp=84871623042&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84871623042&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2001.922170
DO - 10.1109/ISCAS.2001.922170
M3 - Conference contribution
AN - SCOPUS:84871623042
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 65
EP - 68
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Y2 - 6 May 2001 through 9 May 2001
ER -