Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Research output: Chapter in Book/Report/Conference proceedingConference contribution

74 Scopus citations

Abstract

Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guard- bands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2009
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2009
Pages284-289
Number of pages6
DOIs
StatePublished - Apr 20 2009
EventAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan
Duration: Jan 19 2009Jan 22 2009

Other

OtherAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
CountryJapan
CityYokohama
Period1/19/091/22/09

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