ADC

Rakesh Kumar Palani, Ramesh Harjani

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

This chapter presents a 9-bit 2X time-interleaved successive approximation (SAR) analog-to-digital converter (ADC) for high speed applications. The proposed ADC fabricated in TSMC’s 65 nm GP process occupied an area of 0.0338 mm2 and consists of two time-interleaved channels each operating at 110 MS/s. The sampling capacitor is separated from the capacitive DAC array by performing the input and DAC reference subtraction in the current domain rather than as done traditionally in the charge domain. This allows for an extremely small input capacitance of 133 fF. The measured ADC SFDR is 57 dB and the measured ENOB is 7.55 bits at Nyquist rate while using 1.55 mW power from 1 V supply.

Original languageEnglish (US)
Title of host publicationAnalog Circuits and Signal Processing
PublisherSpringer
Pages103-121
Number of pages19
DOIs
StatePublished - 2017

Publication series

NameAnalog Circuits and Signal Processing
ISSN (Print)1872-082X
ISSN (Electronic)2197-1854

Bibliographical note

Publisher Copyright:
© 2017, Springer International Publishing AG.

Keywords

  • Gate Leakage
  • High Frequency Clock
  • Input Capacitance
  • Sampling Capacitor
  • Switch Resistance

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