Algorithms for fast, memory efficient switch-level fault simulation

E. Vandris, G. Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A class of fault simulation algorithms, that have recently been developed for gate-level fault simulation and shown to have several advantages over concurrent fault simulation, are adapted for switch-level fault simulation. High-speed compiled switch-level simulation, is used for circuit evaluation that approaches the speed of gate-level simulation. The fault simulation algorithms are single fault propagation, differential fault simulation, active fault simulation, and parallel active fault simulation. Using these algorithms, minimum memory requirements and high simulation efficiency are achieved, both of which are essential to performing practical fault simulation at the switch-level due to the large number of switch-level faults.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Pages138-143
Number of pages6
ISBN (Print)0818691492, 9780818691492
DOIs
StatePublished - Jan 1 1991
EventProceedings of the 28th ACM/IEEE Design Automation Conference - San Francisco, CA, USA
Duration: Jun 17 1991Jun 21 1991

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

Other

OtherProceedings of the 28th ACM/IEEE Design Automation Conference
CitySan Francisco, CA, USA
Period6/17/916/21/91

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