TY - GEN
T1 - An 8-bit 22-MHz recycling two-step ASIC ADC with integrating sample and hold
AU - Wongkittikriwon, Somsak
AU - Burns, Stanley G.
PY - 1992/1/1
Y1 - 1992/1/1
N2 - A recycling two-step architecture with a very low input current comparator is used to implement an 8-bit ADC with an integrating S/H mat yields a 22 Msps conversion rate with a 10 MHz input. This twostep recycling architecture makes use of a novel switch circuit design reducing the number of components required for the complete ADC. The ADC is realized using 900 transistors on 2-metal, fT = 8.5 GHz, npn BIT ASICs.
AB - A recycling two-step architecture with a very low input current comparator is used to implement an 8-bit ADC with an integrating S/H mat yields a 22 Msps conversion rate with a 10 MHz input. This twostep recycling architecture makes use of a novel switch circuit design reducing the number of components required for the complete ADC. The ADC is realized using 900 transistors on 2-metal, fT = 8.5 GHz, npn BIT ASICs.
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U2 - 10.1109/MWSCAS.1992.271193
DO - 10.1109/MWSCAS.1992.271193
M3 - Conference contribution
AN - SCOPUS:85065742380
T3 - Midwest Symposium on Circuits and Systems
SP - 839
EP - 842
BT - 1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
Y2 - 9 August 1992 through 12 August 1992
ER -