Abstract
Singular value decomposition (SVD) has become a standard linear algebra tool in modern digital signal processing. CORDIC based SVD algorithms are among the most popular SVD algorithms which exhibit good numerical properties. The speed of the sequential algorithms is however limited by the recursive feedback loops in the underlying signal flow graph. The critical loop computation time is proportional to the size of the problem which prohibits pipelined processing. This paper addresses the derivation of parallel architectures for SVD updating algorithms. An algorithm transformation approach based on re-Timing and matrix associativity is presented to drive parallel SVD updating architectures. These architectures have critical loop computation time independent of the problem size and are suitable for CORDIC arithmetic based VLSI implementations.
Original language | English (US) |
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Title of host publication | Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers |
Editors | Michael B. Matthews |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1401-1405 |
Number of pages | 5 |
ISBN (Electronic) | 0780357000, 9780780357006 |
DOIs | |
State | Published - 1999 |
Externally published | Yes |
Event | 33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999 - Pacific Grove, United States Duration: Oct 24 1999 → Oct 27 1999 |
Publication series
Name | Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers |
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Volume | 2 |
Other
Other | 33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999 |
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Country/Territory | United States |
City | Pacific Grove |
Period | 10/24/99 → 10/27/99 |
Bibliographical note
Publisher Copyright:© 1999 IEEE.