Abstract
We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32times;32 test array implemented in a 130nm process.
| Original language | English (US) |
|---|---|
| Article number | 4672036 |
| Pages (from-to) | 121-124 |
| Number of pages | 4 |
| Journal | Proceedings of the Custom Integrated Circuits Conference |
| DOIs | |
| State | Published - 2008 |
| Event | IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: Sep 21 2008 → Sep 24 2008 |
Bibliographical note
Funding Information:Acknowledgments. This paper was co-financed from the European Social Fund, through the Sectoral Operational Programme Human Resources Development 2007-2013, project number POSDRU/159/1.5/S/138907 “Excellence in scientific interdisciplinary research, doctoral and postdoctoral, in the economic, social and medical fields -EXCELIS”, coordinator The Bucharest University of Economic Studies. Also, the authors gratefully acknowledge partial support of this research by Webster University Thailand.