An FPGA implementation of (3,6)-regular low-density parity-check code decoder

Tong Zhang, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

23 Scopus citations


Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approaches that can achieve appropriate trade-offs between hardware complexity and decoding throughput are highly desirable. Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture based on which we implement a 9216-bit, rate-1/2 (3,6)-regular LDPC code decoder on Xilinx FPGA device. This partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10-6 at 2 dB over AWGN channel while performing maximum 18 decoding iterations.

Original languageEnglish (US)
Pages (from-to)530-542
Number of pages13
JournalEurasip Journal on Applied Signal Processing
Issue number6
StatePublished - May 1 2003


  • Decoder
  • Error-correcting coding
  • FPGA
  • Low-density parity-check codes

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