This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The proposed test structure uses high density standard logic gates as detection circuit for sensing Single Event Transients (SETs) that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.