APPLICATION OF A HIERARCHICAL LAYOUT SYSTEM TO VLSI.

Fred Rose

APPLICATION OF A HIERARCHICAL LAYOUT SYSTEM TO VLSI.

Fred Rose

Institute on the Environment

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

A layout methodology that uses a hierarchical approach, starting with global chip planning followed by bottom-up implementation, is described. The concept of stretchable macrocells is the key to effective employment of this methodology. The author discusses an application of this methodology to VLSI.

Original language	English (US)
Title of host publication	Unknown Host Publication Title
Publisher	IEEE
Pages	125-127
Number of pages	3
State	Published - Dec 1 1984

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title = "APPLICATION OF A HIERARCHICAL LAYOUT SYSTEM TO VLSI.",

abstract = "A layout methodology that uses a hierarchical approach, starting with global chip planning followed by bottom-up implementation, is described. The concept of stretchable macrocells is the key to effective employment of this methodology. The author discusses an application of this methodology to VLSI.",

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APPLICATION OF A HIERARCHICAL LAYOUT SYSTEM TO VLSI.

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