Escalating variations in modern CMOS designs have become a threat to Moore's law. While previous works have proposed techniques for tolerating variations by trading reliability for reduced voltage (energy) , the benefits of such techniques are limited, because voltage/reliability tradeoffs in conventional processors often introduce more errors than can be gainfully tolerated . Recent work has proposed circuit and design-level optimizations [14, 15] that manipulate the error rate behavior of a design to increase the potential for energy savings from voltage/reliability tradeoffs. In this paper, we investigate whether architectural optimizations can also manipulate error rate behavior to significantly increase the energy savings from voltage/reliability tradeoffs. To this end, we demonstrate how error rate behavior indeed depends on processor architecture, and that architectural optimizations can be used to manipulate the error rate behavior of a processor. We show that architectural optimizations can significantly enhance voltage/reliability tradeoffs, achieving up to 29% additional energy savings for processors that employ Razor-based error resilience.