Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis∗

Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Synchronization is the key to guaranteeing correct execution of parallel programs at any scale. Barriers represent heavily used synchronization primitives which prevent parallel tasks from proceeding to subsequent stages of computation before all tasks are done with previous stages. Accordingly, all tasks wait at a barrier until the slowest tasks finish, at which point all tasks can proceed to the next stage of computation. This usually translates into an abrupt change in the activity, i.e., current demand from the power delivery network, and if not orchestrated properly, can easily lead to voltage emergencies. In this study we characterize the impact of different barrier structures on voltage noise.

Original languageEnglish (US)
Title of host publicationProceedings of the 2019 IEEE International Symposium on Workload Characterization, IISWC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages263-267
Number of pages5
ISBN (Electronic)9781728140452
DOIs
StatePublished - Nov 2019
Event15th IEEE International Symposium on Workload Characterization, IISWC 2019 - Orlando, United States
Duration: Nov 3 2019Nov 5 2019

Publication series

NameProceedings of the 2019 IEEE International Symposium on Workload Characterization, IISWC 2019

Conference

Conference15th IEEE International Symposium on Workload Characterization, IISWC 2019
Country/TerritoryUnited States
CityOrlando
Period11/3/1911/5/19

Bibliographical note

Funding Information:
This work was supported in part by NSF grant no. CCF-1438286.

Keywords

  • barrier synchronization
  • voltage noise

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