Synchronization is the key to guaranteeing correct execution of parallel programs at any scale. Barriers represent heavily used synchronization primitives which prevent parallel tasks from proceeding to subsequent stages of computation before all tasks are done with previous stages. Accordingly, all tasks wait at a barrier until the slowest tasks finish, at which point all tasks can proceed to the next stage of computation. This usually translates into an abrupt change in the activity, i.e., current demand from the power delivery network, and if not orchestrated properly, can easily lead to voltage emergencies. In this study we characterize the impact of different barrier structures on voltage noise.
|Original language||English (US)|
|Title of host publication||Proceedings of the 2019 IEEE International Symposium on Workload Characterization, IISWC 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||5|
|State||Published - Nov 2019|
|Event||15th IEEE International Symposium on Workload Characterization, IISWC 2019 - Orlando, United States|
Duration: Nov 3 2019 → Nov 5 2019
|Name||Proceedings of the 2019 IEEE International Symposium on Workload Characterization, IISWC 2019|
|Conference||15th IEEE International Symposium on Workload Characterization, IISWC 2019|
|Period||11/3/19 → 11/5/19|
Bibliographical noteFunding Information:
This work was supported in part by NSF grant no. CCF-1438286.
- barrier synchronization
- voltage noise