Dual cycle shift data-weighted averaging technique for multi-bit sigma-delta modulators

Xiaofen Ma; Jian Xu; Xiaobo Wu

doi:10.1109/EDSSC.2009.5394163

Dual cycle shift data-weighted averaging technique for multi-bit sigma-delta modulators

Xiaofen Ma, Jian Xu, Xiaobo Wu

Biomedical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Data weighted averaging (DWA) is the most popular Dynamic Element Matching (DEM) technique to reduce the effects of DAC nonlinearity in multi-bit Sigma-Delta Modulators (MBSDM). However, due to the non-symmetry of the unit-elements in multi-bit DAC, in-band signal-dependent tones always appear when a low oversampling ratio (OSR) is employed in traditional DWA. Therefore, a novel DEM technique, dual cycle shift DWA(DCSDWA), is proposed to deal with the tone problem in this paper. Compared with other modified DWAtechniques, DCSDWAis a more effective one with simple implementation. Using the proposed technique in a 4th-order MBSDM with an OSR of 32, the maximum in-band tone is reduced to 6 dB when a random DAC-element mismatching error of 0.5% is assumed. In addition, it results in a better linearity of signal-to-noise distortion ratio (SNDR) versus different input signal and a wider dynamic range (DR). The simulation results prove that the proposed DCSDWA is suitable for low OSR applications (OSR≥8) with a good performance.

Original language	English (US)
Title of host publication	2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
Pages	174-177
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2009.5394163
State	Published - Dec 1 2009
Event	2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009 - Xi'an, China Duration: Dec 25 2009 → Dec 27 2009

Other

Other	2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009
Country/Territory	China
City	Xi'an
Period	12/25/09 → 12/27/09

Keywords

DAC nonlinearity
Dual cycle shift DWA
Multi-bit sigma-delta modulators

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10.1109/EDSSC.2009.5394163

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Ma, X, Xu, J & Wu, X 2009, Dual cycle shift data-weighted averaging technique for multi-bit sigma-delta modulators. in 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009., 5394163, pp. 174-177, 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009, Xi'an, China, 12/25/09. https://doi.org/10.1109/EDSSC.2009.5394163

@inproceedings{25b1fb36a34a4197a818b7b1b3bdd0e6,

title = "Dual cycle shift data-weighted averaging technique for multi-bit sigma-delta modulators",

abstract = "Data weighted averaging (DWA) is the most popular Dynamic Element Matching (DEM) technique to reduce the effects of DAC nonlinearity in multi-bit Sigma-Delta Modulators (MBSDM). However, due to the non-symmetry of the unit-elements in multi-bit DAC, in-band signal-dependent tones always appear when a low oversampling ratio (OSR) is employed in traditional DWA. Therefore, a novel DEM technique, dual cycle shift DWA(DCSDWA), is proposed to deal with the tone problem in this paper. Compared with other modified DWAtechniques, DCSDWAis a more effective one with simple implementation. Using the proposed technique in a 4th-order MBSDM with an OSR of 32, the maximum in-band tone is reduced to 6 dB when a random DAC-element mismatching error of 0.5% is assumed. In addition, it results in a better linearity of signal-to-noise distortion ratio (SNDR) versus different input signal and a wider dynamic range (DR). The simulation results prove that the proposed DCSDWA is suitable for low OSR applications (OSR≥8) with a good performance.",

keywords = "DAC nonlinearity, Dual cycle shift DWA, Multi-bit sigma-delta modulators",

author = "Xiaofen Ma and Jian Xu and Xiaobo Wu",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/EDSSC.2009.5394163",

language = "English (US)",

isbn = "9781424442980",

pages = "174--177",

booktitle = "2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009",

note = "2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009 ; Conference date: 25-12-2009 Through 27-12-2009",

}

TY - GEN

T1 - Dual cycle shift data-weighted averaging technique for multi-bit sigma-delta modulators

AU - Ma, Xiaofen

AU - Xu, Jian

AU - Wu, Xiaobo

PY - 2009/12/1

Y1 - 2009/12/1

N2 - Data weighted averaging (DWA) is the most popular Dynamic Element Matching (DEM) technique to reduce the effects of DAC nonlinearity in multi-bit Sigma-Delta Modulators (MBSDM). However, due to the non-symmetry of the unit-elements in multi-bit DAC, in-band signal-dependent tones always appear when a low oversampling ratio (OSR) is employed in traditional DWA. Therefore, a novel DEM technique, dual cycle shift DWA(DCSDWA), is proposed to deal with the tone problem in this paper. Compared with other modified DWAtechniques, DCSDWAis a more effective one with simple implementation. Using the proposed technique in a 4th-order MBSDM with an OSR of 32, the maximum in-band tone is reduced to 6 dB when a random DAC-element mismatching error of 0.5% is assumed. In addition, it results in a better linearity of signal-to-noise distortion ratio (SNDR) versus different input signal and a wider dynamic range (DR). The simulation results prove that the proposed DCSDWA is suitable for low OSR applications (OSR≥8) with a good performance.

AB - Data weighted averaging (DWA) is the most popular Dynamic Element Matching (DEM) technique to reduce the effects of DAC nonlinearity in multi-bit Sigma-Delta Modulators (MBSDM). However, due to the non-symmetry of the unit-elements in multi-bit DAC, in-band signal-dependent tones always appear when a low oversampling ratio (OSR) is employed in traditional DWA. Therefore, a novel DEM technique, dual cycle shift DWA(DCSDWA), is proposed to deal with the tone problem in this paper. Compared with other modified DWAtechniques, DCSDWAis a more effective one with simple implementation. Using the proposed technique in a 4th-order MBSDM with an OSR of 32, the maximum in-band tone is reduced to 6 dB when a random DAC-element mismatching error of 0.5% is assumed. In addition, it results in a better linearity of signal-to-noise distortion ratio (SNDR) versus different input signal and a wider dynamic range (DR). The simulation results prove that the proposed DCSDWA is suitable for low OSR applications (OSR≥8) with a good performance.

KW - DAC nonlinearity

KW - Dual cycle shift DWA

KW - Multi-bit sigma-delta modulators

UR - http://www.scopus.com/inward/record.url?scp=77949580349&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77949580349&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2009.5394163

DO - 10.1109/EDSSC.2009.5394163

M3 - Conference contribution

AN - SCOPUS:77949580349

SN - 9781424442980

SP - 174

EP - 177

BT - 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009

T2 - 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009

Y2 - 25 December 2009 through 27 December 2009

ER -

Dual cycle shift data-weighted averaging technique for multi-bit sigma-delta modulators

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