TY - JOUR
T1 - Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic
AU - Zhao, Min
AU - Sapatnekar, Sachin S.
PY - 2000
Y1 - 2000
N2 - In this paper, two problems on domino logic synthesis are addressed. A mapping method that maps the complementary logic cones independently when AND/OR logic is to be implemented, and together using dual-monotonic gates in the case of XOR/XNOR logic, is proposed. The results show up to 28.9% improvement in area and always show the same or better performance in delay over existing approaches. Then, a 0-1 integer programming formulation is provided for the output phase assignment problem for domino logic. It considers the cost difference between two polarities and enables a standard linear programming package to be used to solve the problem. The results show up to 41.0% improvement in area.
AB - In this paper, two problems on domino logic synthesis are addressed. A mapping method that maps the complementary logic cones independently when AND/OR logic is to be implemented, and together using dual-monotonic gates in the case of XOR/XNOR logic, is proposed. The results show up to 28.9% improvement in area and always show the same or better performance in delay over existing approaches. Then, a 0-1 integer programming formulation is provided for the output phase assignment problem for domino logic. It considers the cost difference between two polarities and enables a standard linear programming package to be used to solve the problem. The results show up to 41.0% improvement in area.
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U2 - 10.1109/ISCAS.2000.856323
DO - 10.1109/ISCAS.2000.856323
M3 - Conference article
AN - SCOPUS:0033683885
SN - 0271-4310
VL - 2
SP - II-309-II-312
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000
Y2 - 28 May 2000 through 31 May 2000
ER -