TY - JOUR
T1 - Eliminating the fanout bottleneck in parallel long BCH encoders
AU - Parhi, Keshab K.
PY - 2004
Y1 - 2004
N2 - Long BCH codes can achieve about 0.6dB additional coding gain over Reed-Solomon codes with similar code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fanout, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. In this paper, a novel scheme based on look-ahead computation and retiming is proposed to eliminate the effect of large fanout in parallel long BCH encoders. For a (2047, 1926) code, compared to the original parallel BCH encoder architecture, the modified architecture can achieve a speedup of 132%.
AB - Long BCH codes can achieve about 0.6dB additional coding gain over Reed-Solomon codes with similar code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fanout, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. In this paper, a novel scheme based on look-ahead computation and retiming is proposed to eliminate the effect of large fanout in parallel long BCH encoders. For a (2047, 1926) code, compared to the original parallel BCH encoder architecture, the modified architecture can achieve a speedup of 132%.
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U2 - 10.1109/icc.2004.1313004
DO - 10.1109/icc.2004.1313004
M3 - Conference article
AN - SCOPUS:4143127855
SN - 0536-1486
VL - 5
SP - 2611
EP - 2615
JO - IEEE International Conference on Communications
JF - IEEE International Conference on Communications
T2 - 2004 IEEE International Conference on Communications
Y2 - 20 June 2004 through 24 June 2004
ER -