Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions

Recently proposed probabilistic spin logic (PSL) has offered promising solutions to novel computing applications, including some that have previously been covered by quantum computing. Several task implementations, including invertible logic gate, have been simulated numerically. Here, we report an experimental demonstration of a magnetic tunnel junction (MTJ) based hardware implementation of PSL. The probabilistic bit (p-bit) is the basic element of PSL. In our hardware implementation of a p-bit, two biasing methods, magnetic field and voltage, were used to better tune the characteristics of the MTJ random fluctuations. This addresses the potential system-wide speed limitations that result from the unavoidable device-to-device variation in MTJ fluctuation rates. With the p-bit hardware implementation demonstrated, we built three p-bits and connected them through a resistor network to implement an example PSL, an invertible and gate, which performs exactly as expected.