Recently proposed probabilistic spin logic (PSL) has offered promising solutions to novel computing applications, including some that have previously been covered by quantum computing. Several task implementations, including invertible logic gate, have been simulated numerically. Here, we report an experimental demonstration of a magnetic tunnel junction (MTJ) based hardware implementation of PSL. The probabilistic bit (p-bit) is the basic element of PSL. In our hardware implementation of a p-bit, two biasing methods, magnetic field and voltage, were used to better tune the characteristics of the MTJ random fluctuations. This addresses the potential system-wide speed limitations that result from the unavoidable device-to-device variation in MTJ fluctuation rates. With the p-bit hardware implementation demonstrated, we built three p-bits and connected them through a resistor network to implement an example PSL, an invertible and gate, which performs exactly as expected.
Bibliographical noteFunding Information:
This work was supported in part by the Center for Probabilistic Spin Logic for Low-Energy Boolean and Non-Boolean Computing (CAPSL), one of the Nanoelectronic Computing Research (nCORE) centers as task 2759.001, and in part by a Semiconductor Research Corporation (SRC) Program sponsored by the National Science Foundation (NSF) under Grant 1739635. The work of R. Bloom and Y. Lv was also partially supported by DARPA ERI FRANC program under Grant FA8650-18-2-7868. The authors would like to thank Prof. S. Datta and Dr. K. Camsari for the useful discussions, especially their early insights and inspiration when their teams worked under the support of C-SPIN, one of six SRC STARnet Programs, on this research topic (www.cspin.umn.edu).
© 2010-2012 IEEE.
- Spin electronics
- magnetic logic devices
- magnetic tunnel junctions
- spin torque
- tunneling magnetoresistance