TY - JOUR
T1 - Fast estimation of area-delay trade-offs in circuit sizing
AU - Karandikar, Shrirang K.
AU - Sapatnekar, Sachin S.
PY - 2005
Y1 - 2005
N2 - Appropriately sizing a circuit can improve its performance signicantly. However, this is a time consuming transform, and it is therefore difcult to compare different implementations of a circuit in terms of the cost overhead required for a particular delay target. This paper presents a fast estimator of the complete area-delay trade-off curve of a given circuit, allowing a designer to choose the most appropriate implementation for a given delay. We observe excellent delity with the actual area-delay curves (94.13% correct comparisons), with an average error of 5.76% in the area differences predicted.
AB - Appropriately sizing a circuit can improve its performance signicantly. However, this is a time consuming transform, and it is therefore difcult to compare different implementations of a circuit in terms of the cost overhead required for a particular delay target. This paper presents a fast estimator of the complete area-delay trade-off curve of a given circuit, allowing a designer to choose the most appropriate implementation for a given delay. We observe excellent delity with the actual area-delay curves (94.13% correct comparisons), with an average error of 5.76% in the area differences predicted.
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U2 - 10.1109/ISCAS.2005.1465402
DO - 10.1109/ISCAS.2005.1465402
M3 - Conference article
AN - SCOPUS:31644448859
SN - 0271-4310
SP - 3575
EP - 3578
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1465402
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -