Genetic architecture search for binarized neural networks

Yangyang Chang, Gerald E. Sobelman, Xiaofang Zhou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In order for deep learning applications to run efficiently on low-power edge devices, including mobile and internet-of-things systems, it is important to reduce their computational and memory requirements. Binarized neural networks have shown promise in this area, but these are typically designed using existing architectures based on floating-point number representations. A more promising approach is to apply network architecture search algorithms to find optimized binarized architectures. In this paper, encoding schemes for the genetic algorithm search of binarized networks are described. The simulation results demonstrate the effectiveness of the proposed method.

Original languageEnglish (US)
Title of host publicationProceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019
EditorsFan Ye, Ting-Ao Tang
PublisherIEEE Computer Society
ISBN (Electronic)9781728107356
DOIs
StatePublished - Oct 2019
Event13th IEEE International Conference on ASIC, ASICON 2019 - Chongqing, China
Duration: Oct 29 2019Nov 1 2019

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference13th IEEE International Conference on ASIC, ASICON 2019
Country/TerritoryChina
CityChongqing
Period10/29/1911/1/19

Bibliographical note

Funding Information:
This work was supported in part by Fudan University State Key Lab of ASIC and Systems, under Grant 2018GF016.

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