Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs

Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani

Research output: Contribution to journalArticlepeer-review

23 Scopus citations

Abstract

Reed-Solomon (RS) coders are used for error-control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. Traditionally, RS coders have been implemented using dedicated hardware. This paper considers software-based implementation of RS codecs. A hardware-software codesign approach is used to design the finite field datapath in a domain-specific digital signal processor (DSP) with low-energy RS codecs application in mind. These datapaths are designed to accommodate programmability with respect to the primitive polynomial as well as the field degree m. A novel heterogeneous digit-serial approach is proposed, where the heterogeneity corresponds to the use of different digit sizes in the multiply-accumulate (MAC) and degree reduction (DEGRED) subarrays. The salient feature of this digit-serial approach is that only the digit cells are implemented in hardware and the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations. Efficient scheduling strategies for digit-serial finite field multiplications are presented and applied to the design of low-energy high-performance RS codecs in software. Significant energy and energy-latency reductions can be achieved using the digit-serial datapaths, as compared with the traditional approach where a combined MAC-DEGRED (parallel multiplier) unit is used. It is concluded that for two-error-correcting RS(n, k) codes over finite field GF(28), datapath containing a parallel MAC unit (of digit size eight) and a DEGRED unit with digit size two (or four) leads to RS codecs with the least energy consumption and energy-latency products; with these datapath architectures and appropriate digit-serial scheduling strategies, more than 60% energy reduction and more than one-third energy-latency reduction can be achieved compared with the parallel multiplication datapath-based approach.

Original languageEnglish (US)
Pages (from-to)160-172
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume8
Issue number2
DOIs
StatePublished - 2000

Bibliographical note

Funding Information:
Manuscript received August 20, 1998. This work was supported by the Army Research Office under Grants DA/DAAH-94-G-0405 and DA/DAAG55-98-1-0315. L. Song is with Bell Laboratories, Lucent Technologies, Holmdel, NJ 07733 USA (e-mail: llsong@lucent.com). K. K. Parhi is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: parhi@ece.umn.edu). I. Kuroda and T. Nishitani are with NEC Corporation, Kawasaki, Japan (e-mail: kuroda@dsp.cl.nec.co.jp; takao@mel.cl.nec.co.jp). Publisher Item Identifier S 1063-8210(00)00770-8.

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