High-frequency broadband amplifier ASIC design optimization using pole-zero compensation techniques

Mark J. Mercer; Stanley G. Burns

High-frequency broadband amplifier ASIC design optimization using pole-zero compensation techniques

Mark J. Mercer, Stanley G. Burns

Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

4 Scopus citations

Abstract

The relative performance of a hierarchy of broadband amplifier designs is examined. This design hierarchy consists of an emitter-coupled pair with resistive-shunt loading for baseline comparison, a compound-device amplifier, a compensated series-feedback amplifier, and an actively shunt-peaked amplifier. Both pole-zero compensated amplifiers incorporate compound devices. The circuits are fabricated on Tektronix Inc.'s analog array chip featuring the SH3 process with 6.5 f_T transistors.

Original language	English (US)
Pages (from-to)	3225-3229
Number of pages	5
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
State	Published - Dec 1 1990
Event	1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA Duration: May 1 1990 → May 3 1990

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abstract = "The relative performance of a hierarchy of broadband amplifier designs is examined. This design hierarchy consists of an emitter-coupled pair with resistive-shunt loading for baseline comparison, a compound-device amplifier, a compensated series-feedback amplifier, and an actively shunt-peaked amplifier. Both pole-zero compensated amplifiers incorporate compound devices. The circuits are fabricated on Tektronix Inc.'s analog array chip featuring the SH3 process with 6.5 fT transistors.",

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AB - The relative performance of a hierarchy of broadband amplifier designs is examined. This design hierarchy consists of an emitter-coupled pair with resistive-shunt loading for baseline comparison, a compound-device amplifier, a compensated series-feedback amplifier, and an actively shunt-peaked amplifier. Both pole-zero compensated amplifiers incorporate compound devices. The circuits are fabricated on Tektronix Inc.'s analog array chip featuring the SH3 process with 6.5 fT transistors.

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Y2 - 1 May 1990 through 3 May 1990

ER -

High-frequency broadband amplifier ASIC design optimization using pole-zero compensation techniques

Abstract

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