HIGH SPEED PARALLEL ENCODER/DECODER FOR b-ADJACENT ERROR-CHECKING CODES.

Atul K. Bhatt, Larry L. Kinney

Research output: Contribution to conferencePaperpeer-review

Abstract

Codes for correction and/or detection of errors which can affect b adjacent bits in memories are considered. The class of Reed-Solomon SEC-DED codes is used. The major goal was to determine the complexity of high-speed decoders for these codes. A completely parallel (combinational logic) implementation of a (44, 32) code is given. The complexity and delay of the decoder is not impractical. The implementation is modular based on arithmetic operations over the Galois Field GF(2**b). The basic structure of the encoder/decoder is the same for other code word lengths.

Original languageEnglish (US)
Pages203-207
Number of pages5
StatePublished - Jan 1 2017
EventUSA - Jpn Comput Conf Proc, 3rd - San Francisco, CA, USA
Duration: Oct 10 1978Oct 12 1978

Other

OtherUSA - Jpn Comput Conf Proc, 3rd
CitySan Francisco, CA, USA
Period10/10/7810/12/78

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