Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

Drew C. Ness; Christian J. Hescott; David J Lilja

doi:10.1109/NANOARCH.2007.4400857

Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

Drew C. Ness, Christian J. Hescott, David J Lilja

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

One of the key challenges in nanoelectronics design is the decreasing reliability due to radiation induced single-event upsets. Without detailed device level simulations or physical experimentation, circuit level models can generate misleading reliability information. We present the results from a screening experiment to identify significant parameters in circuit level SEU simulations. We show that cell supply voltage, sizing parameters, and transient waveform descriptions have an important impact on design and should therefore be considered with care in circuit level designs. Larger variations in parameters can lead to soft error rate estimates that vary by more than 4 orders of magnitude, even small variations can lead to 15x variation in soft error rate estimation for a design. We present our methodology for screening and a ranking based on significance of several parameters involved in soft error simulation at the SPICE level.

Original language	English (US)
Title of host publication	2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH
Publisher	IEEE Computer Society
Pages	46-53
Number of pages	8
ISBN (Print)	9781424417919
DOIs	https://doi.org/10.1109/NANOARCH.2007.4400857
State	Published - 2007
Event	2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH - San Jose, CA, United States Duration: Oct 21 2007 → Oct 22 2007

Publication series

Name	2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH

Other

Other	2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH
Country/Territory	United States
City	San Jose, CA
Period	10/21/07 → 10/22/07

Keywords

Circuit level reliability
Plackett and Burman design
Single event upset (SEU)
Soft-error rate (SER)

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10.1109/NANOARCH.2007.4400857

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Ness, D. C., Hescott, C. J., & Lilja, D. J. (2007). Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations. In 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH (pp. 46-53). Article 4400857 (2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH). IEEE Computer Society. https://doi.org/10.1109/NANOARCH.2007.4400857

Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations. / Ness, Drew C.; Hescott, Christian J.; Lilja, David J.
2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH. IEEE Computer Society, 2007. p. 46-53 4400857 (2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ness, DC, Hescott, CJ & Lilja, DJ 2007, Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations. in 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH., 4400857, 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH, IEEE Computer Society, pp. 46-53, 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH, San Jose, CA, United States, 10/21/07. https://doi.org/10.1109/NANOARCH.2007.4400857

Ness DC, Hescott CJ, Lilja DJ. Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations. In 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH. IEEE Computer Society. 2007. p. 46-53. 4400857. (2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH). doi: 10.1109/NANOARCH.2007.4400857

@inproceedings{cb4ae246050c4397877ed85588ed8b27,

title = "Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations",

abstract = "One of the key challenges in nanoelectronics design is the decreasing reliability due to radiation induced single-event upsets. Without detailed device level simulations or physical experimentation, circuit level models can generate misleading reliability information. We present the results from a screening experiment to identify significant parameters in circuit level SEU simulations. We show that cell supply voltage, sizing parameters, and transient waveform descriptions have an important impact on design and should therefore be considered with care in circuit level designs. Larger variations in parameters can lead to soft error rate estimates that vary by more than 4 orders of magnitude, even small variations can lead to 15x variation in soft error rate estimation for a design. We present our methodology for screening and a ranking based on significance of several parameters involved in soft error simulation at the SPICE level.",

keywords = "Circuit level reliability, Plackett and Burman design, Single event upset (SEU), Soft-error rate (SER)",

author = "Ness, {Drew C.} and Hescott, {Christian J.} and Lilja, {David J}",

year = "2007",

doi = "10.1109/NANOARCH.2007.4400857",

language = "English (US)",

isbn = "9781424417919",

series = "2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH",

publisher = "IEEE Computer Society",

pages = "46--53",

booktitle = "2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH",

note = "2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH ; Conference date: 21-10-2007 Through 22-10-2007",

}

TY - GEN

T1 - Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

AU - Ness, Drew C.

AU - Hescott, Christian J.

AU - Lilja, David J

PY - 2007

Y1 - 2007

N2 - One of the key challenges in nanoelectronics design is the decreasing reliability due to radiation induced single-event upsets. Without detailed device level simulations or physical experimentation, circuit level models can generate misleading reliability information. We present the results from a screening experiment to identify significant parameters in circuit level SEU simulations. We show that cell supply voltage, sizing parameters, and transient waveform descriptions have an important impact on design and should therefore be considered with care in circuit level designs. Larger variations in parameters can lead to soft error rate estimates that vary by more than 4 orders of magnitude, even small variations can lead to 15x variation in soft error rate estimation for a design. We present our methodology for screening and a ranking based on significance of several parameters involved in soft error simulation at the SPICE level.

AB - One of the key challenges in nanoelectronics design is the decreasing reliability due to radiation induced single-event upsets. Without detailed device level simulations or physical experimentation, circuit level models can generate misleading reliability information. We present the results from a screening experiment to identify significant parameters in circuit level SEU simulations. We show that cell supply voltage, sizing parameters, and transient waveform descriptions have an important impact on design and should therefore be considered with care in circuit level designs. Larger variations in parameters can lead to soft error rate estimates that vary by more than 4 orders of magnitude, even small variations can lead to 15x variation in soft error rate estimation for a design. We present our methodology for screening and a ranking based on significance of several parameters involved in soft error simulation at the SPICE level.

KW - Circuit level reliability

KW - Plackett and Burman design

KW - Single event upset (SEU)

KW - Soft-error rate (SER)

UR - http://www.scopus.com/inward/record.url?scp=50849141324&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50849141324&partnerID=8YFLogxK

U2 - 10.1109/NANOARCH.2007.4400857

DO - 10.1109/NANOARCH.2007.4400857

M3 - Conference contribution

AN - SCOPUS:50849141324

SN - 9781424417919

T3 - 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH

SP - 46

EP - 53

BT - 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH

PB - IEEE Computer Society

T2 - 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH

Y2 - 21 October 2007 through 22 October 2007

ER -

Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

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