I/O staggering for low-power jitter reduction

Kin Joe Sham, Ramesh Harjani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations


In this paper, we have developed simplified analytical models for far-end crosstalk that points us in a direction to an ultra-low power technique for reducing crosstalk-induced jitter in existing high-speed memory I/O interfaces. This new architecture design introduces variable delays in alternating lines at the transmitter to mitigate crosstalk-induced jitter. The power-efficient technique decreases jitter at the expense of lowering the voltage margin. The architecture has been verified via simulations and direct measurements. Simulation results at 12Gb/s show that staggered I/Os can successfully reduce jitter by 66.7% and widen the eye by 15.0% while only degrading the voltage margin by 19.5%. Measurement results obtained at 600 Mb/s confirm the presented theoretical framework and show the removal of CIJ at the expense of decreasing the voltage margin from 373mV to 215mV.

Original languageEnglish (US)
Title of host publicationProceedings of the 38th European Microwave Conference, EuMC 2008
Number of pages4
StatePublished - Dec 1 2008
Event38th European Microwave Conference, EuMC 2008 - Amsterdam, Netherlands
Duration: Oct 27 2008Oct 31 2008

Publication series

NameProceedings of the 38th European Microwave Conference, EuMC 2008


Other38th European Microwave Conference, EuMC 2008


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