TY - GEN
T1 - Logic and memory design using spin-based circuits
AU - Liang, Zhaoxin
AU - Mankalale, Meghna
AU - Del Bel, Brandon
AU - Sapatnekar, Sachin S.
PY - 2016/3/7
Y1 - 2016/3/7
N2 - The design of logic and memory circuits in emerging spintronics technology offers fertile ground for new ideas and innovations. We first describe methods for optimizing spintronic logic circuits at the level of physical design, including systematic approaches for building standard cell libraries to enable the design of large circuits. Next, we examine issues in the design of spintronic memories and present methods that trade off volatility with error correction to create dense memory arrays.
AB - The design of logic and memory circuits in emerging spintronics technology offers fertile ground for new ideas and innovations. We first describe methods for optimizing spintronic logic circuits at the level of physical design, including systematic approaches for building standard cell libraries to enable the design of large circuits. Next, we examine issues in the design of spintronic memories and present methods that trade off volatility with error correction to create dense memory arrays.
UR - http://www.scopus.com/inward/record.url?scp=84996799478&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84996799478&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2016.7427996
DO - 10.1109/ASPDAC.2016.7427996
M3 - Conference contribution
AN - SCOPUS:84996799478
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 103
EP - 108
BT - 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Y2 - 25 January 2016 through 28 January 2016
ER -