Low complexity design of high speed parallel decision feedback equalizers

Daesun Oh; Keshab K. Parhi

doi:10.1109/ASAP.2006.43

Low complexity design of high speed parallel decision feedback equalizers

Daesun Oh, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

23 Scopus citations

Abstract

This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. It is well known that the DFE is an efficient scheme to suppress intersymbol interference (ISI) in various communication and magnetic recording systems. However, the feedback loop within a DFE limits an upper bound of the achievable high speed in hardware implementation. A straightforward parallel implementation requires more hardware complexity. The novel proposed technique offers significant reduction of hardware complexity of 56% and 80% over the conventional parallel six-tap DFE architectures for 10 Gbps and 20 Gbps throughput, respectively.

Original language	English (US)
Title of host publication	Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
Pages	118-122
Number of pages	5
DOIs	https://doi.org/10.1109/ASAP.2006.43
State	Published - 2006
Event	IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006 - Steamboat Springs, CO, United States Duration: Sep 11 2006 → Sep 13 2006

Publication series

Name	Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
ISSN (Print)	1063-6862

Other

Other	IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
Country/Territory	United States
City	Steamboat Springs, CO
Period	9/11/06 → 9/13/06

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Oh, D., & Parhi, K. K. (2006). Low complexity design of high speed parallel decision feedback equalizers. In Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006 (pp. 118-122). Article 4019502 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors). https://doi.org/10.1109/ASAP.2006.43

Low complexity design of high speed parallel decision feedback equalizers. / Oh, Daesun; Parhi, Keshab K.
Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006. 2006. p. 118-122 4019502 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Oh, D & Parhi, KK 2006, Low complexity design of high speed parallel decision feedback equalizers. in Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006., 4019502, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, pp. 118-122, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006, Steamboat Springs, CO, United States, 9/11/06. https://doi.org/10.1109/ASAP.2006.43

Oh D, Parhi KK. Low complexity design of high speed parallel decision feedback equalizers. In Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006. 2006. p. 118-122. 4019502. (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors). doi: 10.1109/ASAP.2006.43

@inproceedings{b11351cb13c24bb6b402e04e106866b9,

title = "Low complexity design of high speed parallel decision feedback equalizers",

abstract = "This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. It is well known that the DFE is an efficient scheme to suppress intersymbol interference (ISI) in various communication and magnetic recording systems. However, the feedback loop within a DFE limits an upper bound of the achievable high speed in hardware implementation. A straightforward parallel implementation requires more hardware complexity. The novel proposed technique offers significant reduction of hardware complexity of 56% and 80% over the conventional parallel six-tap DFE architectures for 10 Gbps and 20 Gbps throughput, respectively.",

author = "Daesun Oh and Parhi, {Keshab K.}",

year = "2006",

doi = "10.1109/ASAP.2006.43",

language = "English (US)",

isbn = "0769526829",

series = "Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors",

pages = "118--122",

booktitle = "Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006",

note = "IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006 ; Conference date: 11-09-2006 Through 13-09-2006",

}

TY - GEN

T1 - Low complexity design of high speed parallel decision feedback equalizers

AU - Oh, Daesun

AU - Parhi, Keshab K.

PY - 2006

Y1 - 2006

N2 - This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. It is well known that the DFE is an efficient scheme to suppress intersymbol interference (ISI) in various communication and magnetic recording systems. However, the feedback loop within a DFE limits an upper bound of the achievable high speed in hardware implementation. A straightforward parallel implementation requires more hardware complexity. The novel proposed technique offers significant reduction of hardware complexity of 56% and 80% over the conventional parallel six-tap DFE architectures for 10 Gbps and 20 Gbps throughput, respectively.

AB - This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. It is well known that the DFE is an efficient scheme to suppress intersymbol interference (ISI) in various communication and magnetic recording systems. However, the feedback loop within a DFE limits an upper bound of the achievable high speed in hardware implementation. A straightforward parallel implementation requires more hardware complexity. The novel proposed technique offers significant reduction of hardware complexity of 56% and 80% over the conventional parallel six-tap DFE architectures for 10 Gbps and 20 Gbps throughput, respectively.

UR - http://www.scopus.com/inward/record.url?scp=34547398976&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547398976&partnerID=8YFLogxK

U2 - 10.1109/ASAP.2006.43

DO - 10.1109/ASAP.2006.43

M3 - Conference contribution

AN - SCOPUS:34547398976

SN - 0769526829

SN - 9780769526829

T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

SP - 118

EP - 122

BT - Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006

T2 - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006

Y2 - 11 September 2006 through 13 September 2006

ER -

Low complexity design of high speed parallel decision feedback equalizers

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