## Abstract

A new parallel-in-parallel-out bit-level pipelined multiplier is presented to perform multiplication in GF(2^{m}). This new multiplier uses m^{2} basic cells where each cell has 2 2-input AND, 2 2-input XOR and 3 1-bit latches. The system latency of this multiplier is m+1 compared to 3m in previous architectures. The number of latches required per cell has also been reduced from 7 to 3. We also present a bit-level pipelined parallel-in-parallel-out squarer. This squarer has a system latency of [m/2] compared to 3m in previous designs and is 25% more hardware efficient. The critical paths in both these proposed designs are the same as in existing designs.

Original language | English (US) |
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Pages (from-to) | 2747-2750 |

Number of pages | 4 |

Journal | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |

Volume | 4 |

State | Published - Jan 1 1995 |

Event | Proceedings of the 1995 20th International Conference on Acoustics, Speech, and Signal Processing. Part 2 (of 5) - Detroit, MI, USA Duration: May 9 1995 → May 12 1995 |