Low power gate resizing can decrease the power dissipated in a technology mapped circuit while maintaining its critical path. Gate resizing operates as a post-mapping technique for power reduction by replacing some gates, which are faster than necessary, with smaller and slower gates from the underlying gate library. In this paper we propose a new transformation technique for combinational circuits referred to as buffer-redistribution. Buffer-redistribution is then used to model and solve the low-power discrete gate resizing problem in an exact manner in polynomial time and in a noniterative fashion for a complete gate library. Suboptimal solutions are obtained with incomplete gate libraries. In contrast past polynomial time techniques for gate resizing were either based on heuristics or based on much slower iterative exact algorithms. Simulation results on ISCAS85 benchmark circuits demonstrate 2.1%-54.1% power reduction based on the proposed buffer-redistribution based low-power gate resizing. Power savings from 0%-44.13% are demonstrated over the same circuits mapped for minimum area. The time required for resizing varies from 2.77s-1256.76s.