Low-power, Low-storage-overhead chipkill correct via Multi-line error correction

Due to their large memory capacities, many modern servers require chipkill correct, an advanced type of memory error detection and correction, to meet their reliability require-ments. However, existing chipkill-correct solutions incur high power or storage overheads, or both because they use dedicated error-correction resources per codeword to per-form error correction. This requires high overhead for cor-rection and results in high overhead for error detection. We propose a novel chipkill-correct solution, multi-line error cor-rection, that uses resources shared across multiple lines in memory for error correction to reduce the overhead of both error detection and correction. Our evaluations show that the proposed solution reduces memory power by a mean of 27%, and up to 38% with respect to commercial solutions, at a cost of 0.4% increase in storage overhead and minimal impact on reliability.