With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges. The systematic validation approach starts with defining the correct behaviors of the hardware and software components and their interactions. This requires new modeling paradigms that support multiple levels of abstraction. Mutual consistency of models at adjacent levels of abstraction is crucial for manual refinement of models from the full chip level to production register transfer level, which is likely to remain the dominant design methodology of complex microprocessors in the near future. In this paper, we present microprocessor modeling and validation environment (MMV), a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage, and test generation tools. We illustrate the functionalities in MMV by modeling a 32-bit reduced instruction set computer processor at the system, instruction set architecture, and microarchitecture levels. We show by examples how consistency across levels is enforced during modeling and also how to generate constraints for automatic test generation.
|Original language||English (US)|
|Number of pages||14|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Apr 2008|
Bibliographical noteFunding Information:
Manuscript received September 1, 2006; revised March 12, 2007. This work was supported in part by the National Science Foundation under Project CCR-0237947, by the Semiconductor Research Corporation Integrated Systems Grant, by a gift from Intel Corporation, and by the Minnesota Supercomputing Institute.
- Architectural description language
- Model-driven design and validation
- Validation collaterals