TY - GEN
T1 - MMV
T2 - 11th Annual IEEE International High-Level Design Validation and Test Workshop, HLDVT'06
AU - Dingankar, Ajit
AU - Mathaikutty, Deepak A.
AU - Kodakara, Sreekumar V.
AU - Shukla, Sandeep
AU - Lilja, David
PY - 2006
Y1 - 2006
N2 - With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges, The systematic- validation approach starts with defining the correct beliaviors of the hardware and software components and their interactions. This requires a new modeling paradigm that supports multiple levels or abstraction. Mutual consistency of models at adjacent levels is crucial for manual refinement of models from the full chip level to production RTL, which is likely to remain the dominant design methodology of complex microprocessors in the near future." In this work, we present MMV, a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage and test generation tools. We illustrate the functionalities in MMV by modeling a 32 bit RISC processor at the system, instruction set architecture and microarchitecture levels. "We show by examples how consistency across levels is enforced during modefing and also how to generate constraints for automatic test generation.
AB - With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges, The systematic- validation approach starts with defining the correct beliaviors of the hardware and software components and their interactions. This requires a new modeling paradigm that supports multiple levels or abstraction. Mutual consistency of models at adjacent levels is crucial for manual refinement of models from the full chip level to production RTL, which is likely to remain the dominant design methodology of complex microprocessors in the near future." In this work, we present MMV, a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage and test generation tools. We illustrate the functionalities in MMV by modeling a 32 bit RISC processor at the system, instruction set architecture and microarchitecture levels. "We show by examples how consistency across levels is enforced during modefing and also how to generate constraints for automatic test generation.
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U2 - 10.1109/HLDVT.2006.319978
DO - 10.1109/HLDVT.2006.319978
M3 - Conference contribution
AN - SCOPUS:46249090034
SN - 142440679X
SN - 9781424406791
T3 - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
SP - 143
EP - 148
BT - Proceedings - 11th Annual IEEE International High-Level Design Validation and Test Workshop, HLDVT'06
Y2 - 8 November 2006 through 10 November 2006
ER -