Negative differential conductance in lateral double-barrier transistors fabricated in strained Si quantum wells

The operation of a laterally patterned negative differential conductance (NDC) device based on hot-electron effects in strained Si quantum wells is demonstrated. The device consists of a small, etch-defined dot region connected to narrow leads on either side via point-contact tunnel barriers. The entire device is fabricated on a high-mobility Si/Si_1-xGe_x heterostructure wafer using electron-beam lithography and low-damage reactive-ion etching. At T=0.4 K (T=1.3 K), the drain characteristic of this device shows a pronounced NDC region with a peak-to-valley ratio (PVR) greater than 600 (100). The PVR is reduced with increasing temperature, with remnants of the NDC observable to 30 K. The NDC is attributed to phonon emission by hot electrons injected into the dot region.