Multistage interconnection networks (MIN's) have long been studied for use in switching networks. Since they have a unique path between source and destination and the intermediate nodes of the paths are shared, internal blocking can cause very poor throughput. This paper proposes a high throughput ATM switch consisting of an Omega network with a new form of input queues called bypass queues. We also improve the switch throughput by partitioning the input buffers into disjoint buffer sets and multiplexing several sets of nonblocking cells within a time slot, assuming that the routing switch operates only a couple of times faster than the transmission rate. A neural network model is presented as a controller for cell scheduling and multiplexing in the switch. Our simulation results under uniform traffic show that the proposed approach achieves almost 100% of potential switch throughput.
Bibliographical noteFunding Information:
Manuscript received September 10, 1993; revised June 10, 1994. This work was supported in part by Samsung Electronics Ltd. The authors are with the Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455 USA. IEEE Log Number 9405928.