TY - JOUR
T1 - Overlapped message passing for quasi-cyclic low-density parity check codes
AU - Chen, Yanni
AU - Parhi, Keshab K.
PY - 2004/6/1
Y1 - 2004/6/1
N2 - In this paper, a systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm, namely, check node update and variable node update, could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about twice assuming dual-port memory is available.
AB - In this paper, a systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm, namely, check node update and variable node update, could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about twice assuming dual-port memory is available.
KW - High throughput
KW - Low-density parity check (LDPC) codes
KW - Overlapped message passing (MP)
KW - Quasi-cyclic codes
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U2 - 10.1109/TCSI.2004.826194
DO - 10.1109/TCSI.2004.826194
M3 - Article
AN - SCOPUS:3042549356
VL - 51
SP - 1106
EP - 1113
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 6
ER -