In this paper, a systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm, namely, check node update and variable node update, could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about twice assuming dual-port memory is available.
|Original language||English (US)|
|Number of pages||8|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - Jun 2004|
Bibliographical noteFunding Information:
Manuscript received June 11, 2003; revised December 6, 2003. This work was supported by the Army Research Office under Grant DA/DAAD19-01-1-0705. This paper was presented in part at the ACM Great Lake Symposium on VLSI, April 26–29, 2003, Washington, DC. This paper was recommended by Associate Editor Y. Wang.
- High throughput
- Low-density parity check (LDPC) codes
- Overlapped message passing (MP)
- Quasi-cyclic codes