p-Type SiGe transistors with low gate leakage using SiN gate dielectric

W. Lu, X. W. Wang, R. Hammond, A. Kuliev, S. Koester, J. O. Chu, K. Ismail, T. P. Ma, I. Adesida

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

Using high-quality jet-vapor-deposited (JVD) SiN as gate dielectric, p-type SiGe transistors are fabricated on SiGe heterostructures grown by ultra-high-vacuum chemical vapor deposition (UHVCVD). For an 0.25-μm gate-length device, the gate leakage current is as small as 2.4 nA/mm at Vds = -1.0 V and Vgs = 0.4 V. A maximum extrinsic transconductance of 167 mS/mm is measured. A unity current gain cutoff frequency of 27 GHz and a maximum oscillation frequency of 45 GHz are obtained.

Original languageEnglish (US)
Pages (from-to)514-516
Number of pages3
JournalIEEE Electron Device Letters
Volume20
Issue number10
DOIs
StatePublished - Oct 1999

Bibliographical note

Funding Information:
Manuscript received April 7, 1999; revised June 15, 1999. This work was supported by DARPA Grant N66001-97-1-8906 (AME Program) and National Science Foundation ECS Grant 97-10418. W. Lu, A. Kuliev, and I. Adesida are with Microelectronics Laboratory, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. X. W. Wang and T. P. Ma are with the Department of Electrical Engineering, Yale University, New Haven, CT 06520 USA. R. Hammond, S. Koester, J. O. Chu, and K. Ismail are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. Publisher Item Identifier S 0741-3106(99)07850-7.

Copyright:
Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.

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