Parallel resonant DC link circuit - A novel zero switching loss topology with minimum voltage stresses

Jin He, Ned Mohan

Research output: Contribution to journalConference articlepeer-review

22 Scopus citations

Abstract

A parallel-resonant DC link (PRDCL) circuit topology is presented as a way to realizing zero-switching-loss, DC-AC high-switching-frequency power conversion. The circuit is used as an interface between DC voltage supply and the voltage-source PWM (pulse-width-modulated) inverter. It provides a short zero-voltage period in the DC link of the inverter to allow zero-voltage switching to take place in the PWM inverter. The peak voltage stress on the PWM inverter switches is limited to the DC supply voltage. Another significant advantage of the proposed circuit is that the inverter can be controlled by the conventional PWM strategy. The circuit is systematically analyzed, and its operation principle is explained in detail. Design considerations and formulas are also presented. A complete zero-voltage-switching DC-AC system consisting of the proposed circuit and the PWM inverter is simulated on computer.

Original languageEnglish (US)
Pages (from-to)1006-1012
Number of pages7
JournalPESC Record - IEEE Annual Power Electronics Specialists Conference
Volume2
StatePublished - 1989
Event20th Annual IEEE Power Electronics Specialists Conference - PESC '89 - Milwaukee, WI, USA
Duration: Jun 26 1989Jun 29 1989

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