Performance tradeoffs in digit-serial DSP systems

Hiroshi Suzuki, Yun Nan Chang, Keshab K. Parhi

Research output: Contribution to journalConference articlepeer-review

10 Scopus citations

Abstract

This paper addresses performance tradeoffs in digit-serial arithmetic architectures for design of dedicated and programmable DSP systems. The advantages and the disadvantages of the digit-serial approach over bit-parallel approach are discussed in terms of area, latency and power consumption. The addition and the multiplication are chosen for comparison. Digit-serial adders have a significant area advantage over bit-parallel adders. Digit-serial multipliers, however, have less area advantage due to large number of feedback registers. In addition, critical paths of digit-serial multipliers cannot be reduced significantly compared to low-latency bit-parallel multipliers such as the Wallace tree multiplier. Quantitative performance tradeoffs in design of both programmable and dedicated DSP systems are considered. It is shown that the digit-serial arithmetic is not suitable for programmable DSPs. However, dedicated DSPs can be successfully implemented with the digit-serial arithmetic in limited silicon area.

Original languageEnglish (US)
Pages (from-to)1225-1229
Number of pages5
JournalConference Record of the Asilomar Conference on Signals, Systems and Computers
Volume2
StatePublished - Dec 1 1998
EventProceedings of the 1998 32nd Asilomar Conference on Signals, Systems & Computers. Part 1 (of 2) - Pacific Grove, CA, USA
Duration: Nov 1 1998Nov 4 1998

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