Reduced-order Aggregate Model for Parallel-connected Single-phase Inverters

Victor Purba, Brian B. Johnson, Miguel Rodriguez, Saber Jafarpour, Francesco Bullo, Sairaj V. Dhople

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

This paper outlines a reduced-order aggregate dynamical model for parallel-connected single-phase grid-connected inverters. For each inverter, we place no restrictions on the converter topology and merely assume that the ac-side switch-averaged voltage can be controlled via pulsewidth modulation. The ac output of each inverter interfaces through an LCL filter to the grid. The closed-loop system contains a phase locked loop for grid synchronization, and real- and reactive-power control are realized with inner and outer PI current- and power-control loops. We derive a necessary and sufficient set of parametric relationships to ensure that a reduced-order aggregated state-space model for an arbitrary number of such paralleled inverters has the same model order and structure as any single inverter. We also present reduced-order models for the settings where the real- and reactive-power setpoints are different and where the inverters have different power ratings. We anticipate the proposed model being useful in analyzing the dynamics of large collections of parallel-connected inverters with minimal computational complexity. The aggregate model is validated against measurements obtained from a multi-inverter experimental setup consisting of three {\text{750-VA}} paralleled grid-connected inverters, hence establishing robustness of the analytical result to parametric variations seen in practice.

Original languageEnglish (US)
Article number8537786
Pages (from-to)824-837
Number of pages14
JournalIEEE Transactions on Energy Conversion
Volume34
Issue number2
DOIs
StatePublished - Jun 2019

Bibliographical note

Funding Information:
Manuscript received March 8, 2018; revised July 24, 2018 and September 24, 2018; accepted November 11, 2018. Date of publication November 16, 2018; date of current version May 2, 2019. This work was supported in part by the U.S. Department of Energy under Contract DE-EE0000-1583 and in part by the National Science Foundation under Grant 1453921. Paper no. TEC-00217-2018.R2. (Corresponding author: Sairaj V. Dhople.) V. Purba and S. V. Dhople are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail:, purba002@umn.edu; sdhople@umn.edu).

Funding Information:
This work was supported in part by the U.S. Department of Energy under Contract DE-EE0000-1583 and in part by the National Science Foundation under Grant 1453921. Paper no. TEC-00217- 2018.R2.

Publisher Copyright:
© 1986-2012 IEEE.

Keywords

  • Model reduction
  • phase-locked loop
  • single-phase inverter
  • voltage-source inverter

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