SiGe BiCMOS PAM-4 clock and data recovery circuit for high-speed serial communications

Ming Ta Hsieh; G. E. Sobelman

doi:10.1109/SOC.2003.1241531

SiGe BiCMOS PAM-4 clock and data recovery circuit for high-speed serial communications

Ming Ta Hsieh, G. E. Sobelman

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

A multilevel clock and data recovery (CDR) circuit for highspeed serial data transmission was designed using the IBM 6 HP 0.25 μm SiGe BiCMOS process technology. The circuit extracts the clock from a 32 Gb/s 4-level pulse amplitude modulated (PAM-4) input signal and outputs four channels of retimed NRZ data at 8 Gb/s per channel. The CDR design incorporates a PAM-4 to 2-bit-binary converter, a phase/frequency detector, a loop filter, a quadrature LC ring oscillator and a data-retiming module. The circuit operates using a 3.3 V supply voltage with a 350 mA current consumption. The simulation results show that the peak-to-peak jitter is 1.3 ps, the capture range is 2 GHz, the acquisition time is 200 ns and the input sensitivity is 150 mV. This PAM-based CDR technique is quite suitable for low-loss transmission channels such as fiber optic communications or short-distance copper links, including network-on-chip (NOC) implementations and storage area networks (SANs).

Original language	English (US)
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2003
Editors	Dong S. Ha, Richard Auletta, John Chickanosky
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	305-308
Number of pages	4
ISBN (Electronic)	0780381823, 9780780381827
DOIs	https://doi.org/10.1109/SOC.2003.1241531
State	Published - 2003
Event	IEEE International SOC Conference, SOCC 2003 - Portland, United States Duration: Sep 17 2003 → Sep 20 2003

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2003

Other

Other	IEEE International SOC Conference, SOCC 2003
Country	United States
City	Portland
Period	9/17/03 → 9/20/03

Keywords

Amplitude modulation
BiCMOS integrated circuits
Clocks
Data communication
Data mining
Germanium silicon alloys
Network-on-a-chip
Pulse circuits
Pulse modulation
Silicon germanium

Access

10.1109/SOC.2003.1241531

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Hsieh, M. T., & Sobelman, G. E. (2003). SiGe BiCMOS PAM-4 clock and data recovery circuit for high-speed serial communications. In D. S. Ha, R. Auletta, & J. Chickanosky (Eds.), Proceedings - IEEE International SOC Conference, SOCC 2003 (pp. 305-308). [1241531] (Proceedings - IEEE International SOC Conference, SOCC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOC.2003.1241531

SiGe BiCMOS PAM-4 clock and data recovery circuit for high-speed serial communications. / Hsieh, Ming Ta; Sobelman, G. E.

Proceedings - IEEE International SOC Conference, SOCC 2003. ed. / Dong S. Ha; Richard Auletta; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. p. 305-308 1241531 (Proceedings - IEEE International SOC Conference, SOCC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hsieh, MT & Sobelman, GE 2003, SiGe BiCMOS PAM-4 clock and data recovery circuit for high-speed serial communications. in DS Ha, R Auletta & J Chickanosky (eds), Proceedings - IEEE International SOC Conference, SOCC 2003., 1241531, Proceedings - IEEE International SOC Conference, SOCC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 305-308, IEEE International SOC Conference, SOCC 2003, Portland, United States, 9/17/03. https://doi.org/10.1109/SOC.2003.1241531

Hsieh MT, Sobelman GE. SiGe BiCMOS PAM-4 clock and data recovery circuit for high-speed serial communications. In Ha DS, Auletta R, Chickanosky J, editors, Proceedings - IEEE International SOC Conference, SOCC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 305-308. 1241531. (Proceedings - IEEE International SOC Conference, SOCC 2003). https://doi.org/10.1109/SOC.2003.1241531

Hsieh, Ming Ta ; Sobelman, G. E. / SiGe BiCMOS PAM-4 clock and data recovery circuit for high-speed serial communications. Proceedings - IEEE International SOC Conference, SOCC 2003. editor / Dong S. Ha ; Richard Auletta ; John Chickanosky. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 305-308 (Proceedings - IEEE International SOC Conference, SOCC 2003).

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abstract = "A multilevel clock and data recovery (CDR) circuit for highspeed serial data transmission was designed using the IBM 6 HP 0.25 μm SiGe BiCMOS process technology. The circuit extracts the clock from a 32 Gb/s 4-level pulse amplitude modulated (PAM-4) input signal and outputs four channels of retimed NRZ data at 8 Gb/s per channel. The CDR design incorporates a PAM-4 to 2-bit-binary converter, a phase/frequency detector, a loop filter, a quadrature LC ring oscillator and a data-retiming module. The circuit operates using a 3.3 V supply voltage with a 350 mA current consumption. The simulation results show that the peak-to-peak jitter is 1.3 ps, the capture range is 2 GHz, the acquisition time is 200 ns and the input sensitivity is 150 mV. This PAM-based CDR technique is quite suitable for low-loss transmission channels such as fiber optic communications or short-distance copper links, including network-on-chip (NOC) implementations and storage area networks (SANs).",

keywords = "Amplitude modulation, BiCMOS integrated circuits, Clocks, Data communication, Data mining, Germanium silicon alloys, Network-on-a-chip, Pulse circuits, Pulse modulation, Silicon germanium",

author = "Hsieh, {Ming Ta} and Sobelman, {G. E.}",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE. Copyright: Copyright 2015 Elsevier B.V., All rights reserved.; IEEE International SOC Conference, SOCC 2003 ; Conference date: 17-09-2003 Through 20-09-2003",

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AB - A multilevel clock and data recovery (CDR) circuit for highspeed serial data transmission was designed using the IBM 6 HP 0.25 μm SiGe BiCMOS process technology. The circuit extracts the clock from a 32 Gb/s 4-level pulse amplitude modulated (PAM-4) input signal and outputs four channels of retimed NRZ data at 8 Gb/s per channel. The CDR design incorporates a PAM-4 to 2-bit-binary converter, a phase/frequency detector, a loop filter, a quadrature LC ring oscillator and a data-retiming module. The circuit operates using a 3.3 V supply voltage with a 350 mA current consumption. The simulation results show that the peak-to-peak jitter is 1.3 ps, the capture range is 2 GHz, the acquisition time is 200 ns and the input sensitivity is 150 mV. This PAM-based CDR technique is quite suitable for low-loss transmission channels such as fiber optic communications or short-distance copper links, including network-on-chip (NOC) implementations and storage area networks (SANs).

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KW - Silicon germanium

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