Abstract
An important link between individual component-level EM failures and the failure of the associated system is established in this work. Conventional EM methodologies are based on the weakest link assumption, which deems the entire system to fail as soon as the first component in the system fails. With a highly redundant circuit topology - that of a clock grid - we present algorithms for EM assessment, which allow us to incorporate and quantify the benefit from system redundancies. We demonstrate that unless such an analysis is performed, chip lifetimes are underestimated by over 2x.
Original language | English (US) |
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Title of host publication | 2015 IEEE International Reliability Physics Symposium, IRPS 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 3D41-3D46 |
ISBN (Electronic) | 9781467373623 |
DOIs | |
State | Published - May 26 2015 |
Event | IEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States Duration: Apr 19 2015 → Apr 23 2015 |
Publication series
Name | IEEE International Reliability Physics Symposium Proceedings |
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Volume | 2015-May |
ISSN (Print) | 1541-7026 |
Other
Other | IEEE International Reliability Physics Symposium, IRPS 2015 |
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Country/Territory | United States |
City | Monterey |
Period | 4/19/15 → 4/23/15 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
Keywords
- clock
- clock-grid
- delay-degradation
- electromigration
- skew