Stochastic and topologically aware electromigration analysis for clock skew

Palkesh Jain, Sachin S Sapatnekar, Jordi Cortadella

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

An important link between individual component-level EM failures and the failure of the associated system is established in this work. Conventional EM methodologies are based on the weakest link assumption, which deems the entire system to fail as soon as the first component in the system fails. With a highly redundant circuit topology - that of a clock grid - we present algorithms for EM assessment, which allow us to incorporate and quantify the benefit from system redundancies. We demonstrate that unless such an analysis is performed, chip lifetimes are underestimated by over 2x.

Original languageEnglish (US)
Title of host publication2015 IEEE International Reliability Physics Symposium, IRPS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages3D41-3D46
Volume2015-May
ISBN (Electronic)9781467373623
DOIs
StatePublished - Jan 1 2015
EventIEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States
Duration: Apr 19 2015Apr 23 2015

Other

OtherIEEE International Reliability Physics Symposium, IRPS 2015
Country/TerritoryUnited States
CityMonterey
Period4/19/154/23/15

Keywords

  • clock
  • clock-grid
  • delay-degradation
  • electromigration
  • skew

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