Abstract
The main advantages of a switch-mode var compensator (SMVC) which employs a voltage source force-commutated inverter include minimum energy storage elements, continuous and fast reactive power control. However, various problems still exist. The main problems are device switching losses and electromagnetic interference (EMI) since the devices in the inverter operate in a force-commutated mode. To minimize these problems, this paper proposes a so-called parallei-resonant dc link (PRDCL) circuit topology as an interface between dc voltage supply and the inverter to provide a short zero voltage period in the dc link of the inverter to allow zero voltage switchings in the SMVC. The proposed circuit along with SMVC can compensate for leading and lagging displacement power factor with a high switching frequency at singificantly reduced switching losses. The new circuit is especially suitable for high power SMVC applications using GTOs or other gate turn-off devices. The proposed circuit is analyzed in detail and its operation principle is explained. Several design considerations are addressed and the design formulas are obtained. The new topology and the overall system are verified by computer simulations.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 90-95 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Power Systems |
| Volume | 5 |
| Issue number | 1 |
| DOIs | |
| State | Published - Feb 1990 |
Bibliographical note
Funding Information:The authors grdtefully acknowledge the financial support from the University of :-linnesota Center for Electric Energy, sponsored by the Minnesota/Wisconsin Power Suppliers group.
