System-Level Power Analysis of a Multicore Multipower Domain Processor with ON-Chip Voltage Regulators

Ayan Paul; Sang Phill Park; Dinesh Somasekhar; Young Moon Kim; Nitin Borkar; Ulya R. Karpuzcu; Chris H. Kim

doi:10.1109/TVLSI.2016.2555954

System-Level Power Analysis of a Multicore Multipower Domain Processor with ON-Chip Voltage Regulators

Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

In this paper, we study two different ON-chip power delivery schemes, namely, fully integrated voltage regulator (FIVR) and low-dropout regulator (LDO), and analyze their effect on total system power under process variation, assuming a realistic dynamic voltage-frequency scaling (DVFS) system. The impact of different task scheduling algorithms on the overall system power was also analyzed. We find that in a hypothetical 256-core processor, under a per-core DVFS assumption, the FIVR-based power delivery consumes 20% less power than the LDO-based one for a 50% throughput. However, as the number of cores in the processor reduces, the difference in power consumption between the FIVR-based and LDO-based power delivery schemes becomes smaller. For example, in the case of a 16-core processor with per-core DVFS capability, FIVR-based design was found to consume about the same power as the LDO-based design.

Original language	English (US)
Article number	7468580
Pages (from-to)	3468-3476
Number of pages	9
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	24
Issue number	12
DOIs	https://doi.org/10.1109/TVLSI.2016.2555954
State	Published - Dec 2016

Bibliographical note

Funding Information:
This work was supported by the U.S. Department of Energy, Office of Science, and the National Nuclear Security Administration through the FastFoward program at the Lawrence Livermore National Laboratory under Contract B600738.

Publisher Copyright:
© 2016 IEEE.

Keywords

Circuit simulation
dynamic voltage scaling
integrated circuit modeling
multicore processing
power dissipation
regulators
switching converters

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title = "System-Level Power Analysis of a Multicore Multipower Domain Processor with ON-Chip Voltage Regulators",

abstract = "In this paper, we study two different ON-chip power delivery schemes, namely, fully integrated voltage regulator (FIVR) and low-dropout regulator (LDO), and analyze their effect on total system power under process variation, assuming a realistic dynamic voltage-frequency scaling (DVFS) system. The impact of different task scheduling algorithms on the overall system power was also analyzed. We find that in a hypothetical 256-core processor, under a per-core DVFS assumption, the FIVR-based power delivery consumes 20% less power than the LDO-based one for a 50% throughput. However, as the number of cores in the processor reduces, the difference in power consumption between the FIVR-based and LDO-based power delivery schemes becomes smaller. For example, in the case of a 16-core processor with per-core DVFS capability, FIVR-based design was found to consume about the same power as the LDO-based design.",

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System-Level Power Analysis of a Multicore Multipower Domain Processor with ON-Chip Voltage Regulators

Abstract

Bibliographical note

Keywords

UN SDGs

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