Abstract
Single-fault, multi-fault, 0-1 static sensitizable path and robust path delay fault are often used to measure the testability of a circuit. In this paper, we explore the relationships among these testabilities. In addition to the relationships discovered before, we have proved that 100% single fault testability, 100% 0-1 static sensitizability are equivalent in two-level single-output circuits. We have also proved that 100% 0-1 static sensitizability implies 100% multi-fault testability, and that 100% robust path delay fault testability implies 100% multi-fault testability in two-level circuits. Several new conditions for gate merging while keeping 100% single-fault testability are presented. We further proved that the three transformations D1,1,2, extraction, De-Morgan keeping 100% single fault testability also preserve 100% multiple-fault testability, 100% multi-fault testability, 100% robust path delay fault testability. We have answered the following two open questions in this paper: 1) Does 100% multi-fault testability in a multiple outputs circuit not require 100% 0-1 static sensitizability? 2) Does 100% multi-fault testability in a single output circuit imply 100% 0-1 static sensitizability?
| Original language | English (US) |
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| Title of host publication | Proceedings - IEEE International Conference on Computer Design |
| Subtitle of host publication | VLSI in Computers and Processors |
| Editors | Anon |
| Publisher | IEEE |
| Pages | 97-100 |
| Number of pages | 4 |
| State | Published - Dec 1 1994 |
| Event | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA Duration: Oct 10 1994 → Oct 12 1994 |
Other
| Other | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors |
|---|---|
| City | Cambridge, MA, USA |
| Period | 10/10/94 → 10/12/94 |