TY - GEN
T1 - The analysis of cyclic circuits with boolean satisfiability
AU - Backes, John
AU - Fett, Brian
AU - Riedel, Marc
PY - 2008
Y1 - 2008
N2 - The accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forward) topologies. And yet simple examples suggest that this need not be so. In previous work, we advocated the design of cyclic combinational circuits (i.e., circuits with loops or feedback paths). We proposed a synthesis methodology and demonstrated that it produces significant improvements in area and in delay. The analysis method that we used to validate cyclic circuits was based on binary decision diagrams. In this paper, we propose a much more efficient technique for analysis based on Boolean satisfiability (SAT).
AB - The accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forward) topologies. And yet simple examples suggest that this need not be so. In previous work, we advocated the design of cyclic combinational circuits (i.e., circuits with loops or feedback paths). We proposed a synthesis methodology and demonstrated that it produces significant improvements in area and in delay. The analysis method that we used to validate cyclic circuits was based on binary decision diagrams. In this paper, we propose a much more efficient technique for analysis based on Boolean satisfiability (SAT).
UR - http://www.scopus.com/inward/record.url?scp=57849144694&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=57849144694&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2008.4681565
DO - 10.1109/ICCAD.2008.4681565
M3 - Conference contribution
AN - SCOPUS:57849144694
SN - 9781424428205
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 143
EP - 148
BT - 2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008
T2 - 2008 International Conference on Computer-Aided Design, ICCAD
Y2 - 10 November 2008 through 13 November 2008
ER -