The analysis of cyclic circuits with boolean satisfiability

John Backes, Brian Fett, Marc Riedel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

The accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forward) topologies. And yet simple examples suggest that this need not be so. In previous work, we advocated the design of cyclic combinational circuits (i.e., circuits with loops or feedback paths). We proposed a synthesis methodology and demonstrated that it produces significant improvements in area and in delay. The analysis method that we used to validate cyclic circuits was based on binary decision diagrams. In this paper, we propose a much more efficient technique for analysis based on Boolean satisfiability (SAT).

Original languageEnglish (US)
Title of host publication2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008
Pages143-148
Number of pages6
DOIs
StatePublished - Dec 26 2008
Event2008 International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States
Duration: Nov 10 2008Nov 13 2008

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

Other2008 International Conference on Computer-Aided Design, ICCAD
CountryUnited States
CitySan Jose, CA
Period11/10/0811/13/08

Fingerprint Dive into the research topics of 'The analysis of cyclic circuits with boolean satisfiability'. Together they form a unique fingerprint.

Cite this