The impact of electromigration in copper interconnects on power grid integrity

Vivek Mishra, Sachin S. Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

35 Scopus citations

Abstract

Electromigration (EM), a growing problem in on-chip interconnects, can cause wire resistances in a circuit to increase under stress, to the point of creating open circuits. Classical circuit-level EM models have two drawbacks: first, they do not accurately capture the physics of degradation in copper dual-damascene (CuDD) metallization, and second, they fail to model the inherent resilience in a circuit that keeps it functioning even after a wire fails. This work overcomes both limitations. For a single wire, our probabilistic analysis encapsulates known realities about CuDD wires, e.g., that some regions of these wires are more susceptible to EM than others, and that void formation/growth show statistical behavior. We apply these ideas to the analysis of on-chip power grids and demonstrate the inherent robustness of these grids that maintains supply integrity under some EM failures.

Original languageEnglish (US)
Title of host publicationProceedings of the 50th Annual Design Automation Conference, DAC 2013
DOIs
StatePublished - 2013
Event50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States
Duration: May 29 2013Jun 7 2013

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other50th Annual Design Automation Conference, DAC 2013
Country/TerritoryUnited States
CityAustin, TX
Period5/29/136/7/13

Keywords

  • Electromigration
  • Power grid
  • Process variation
  • Robustness

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